Up to now, semiconductor devices having the SJ structure in which n-type columns and p-type columns are alternately repetitively formed have been known (for example, refer to PTL 1). In manufacturing the semiconductor device of the SJ structure, for example, as illustrated in FIG. 9A, a semiconductor substrate J3 in which an n− type layer J2 is epitaxially grown on a surface of an n+ type silicon substrate J1 is used. After trenches J4 have been formed in the n− type layer J2 as illustrated in FIG. 9B, a p− type layer J5 is epitaxially grown within the trenches J4 as illustrated in FIG. 9C. Then, as illustrated in FIG. 10A, the p− type layer J5 formed outside the trenches J4 is removed by flattening and polishing the surface to leave the p− type layer J5 only within the trenches J4. As a result, the SJ structure having a PN column in which n type columns formed of the n− type layer J2 and p− type columns formed of the p− type layer J5 are alternately repeated is formed.
Thereafter, as illustrated in FIG. 10B, after the SJ structure has been formed, a p− type layer J6 is epitaxially grown, and then a subsequent device forming process is conducted. For example, as illustrated in FIG. 10C, a process of forming an n+ type source region J7, a trench gate structure J8, a surface electrode J9, and a back surface electrode J10 is performed in the same technique as that in the conventional art. Through this technique, the vertical MOS transistor of the SJ structure is manufactured.
However, the flattening and polishing of surfaces of the p− type layer J5 and the n− type layer J2 is performed after the p− type layer J5 has been epitaxially grown so as to fill in the trenches J4. A variation in the flattening and polishing is large, and depths of the PN columns are varied, and cannot reach a desired depth with high precision. Aside from a problem on a precision of the epitaxial growth per se, this is further because the flattening and polishing of the p− type layer J5 and the n− type layer J2 is performed by a process for polishing the same semiconductor material (for example, silicon), and it is difficult to stop the polishing with a target film thickness in principle. When the depths of the PN columns are thus varied, a breakdown voltage of the semiconductor device is varied resulting in such a problem that the device characteristics are deteriorated.
The p− type layer J6 is epitaxially grown on the SJ structure after the SJ structure has been formed. However, there also arises such a problem that processing between structures of the surface of the SJ structure and the p− type layer J6 causes the p− type layer J6 on an upper side thereof to abnormally grow, resulting in the deterioration of the device characteristics. In the present specification, the processing between the structures means the flattening and polishing of the surface of the SJ structure after the SJ structure has been formed, and wafer cleaning before the growth of the p− type layer J6. Crystal defects may occur depending on this processing, and the crystal defects may be taken over to abnormally grow the p-type layer.
Since the process of forming the p− type layer J6 is performed, independently, there also arises such a problem that the manufacturing costs rise with an increase in the number of manufacturing processes.